Conventionally, there is available a digital amplifier called “D-class amplifier” as an audio power amplifier. The D-class amplifier amplifies a power by switching, and it is constructed as shown in FIG. 1 for example.
In the power amplifier shown in FIG. 1, digital audio signal Pin is supplied to a PWM circuit 11 via an input terminal Tin, and clock signal having a predetermined frequency is supplied from a clock generator 12 to the PWM circuit 11. The digital audio signal Pin supplied to the PWM circuit 11 is converted into a pair of PWM signals PA and PB.
As shown in FIGS. 2A and 2B the pulse width of the PWM signals PA and PB, or a time duration for which the waveform of each PWM signal keeps “H” level, varies correspondingly to a quantization level the digital audio signal Pin takes (corresponding to a momentary level of the signal Pin when the signal is converted from digital to analog). The pulse width of one of the PWM signal PA corresponds to the magnitude of the quantization level the digital audio signal Pin itself takes, while the pulse width of the other PWM signal PB corresponds to the magnitude of two's complement of the quantization level the digital audio signal Pin takes.
Note that the PWM signals PA and PB shown in FIGS. 2A and 2B rise only at the start time point of one time cycle (reference period) TC of the PWM signals PA and PB, and falls at a time point varying correspondingly to a level the digital audio signal Pin takes. That is, the PWM signals PA and PB are a so-called unilateral modulation signal.
The PWM signals PA and PB may be a so-called bilateral modulation signal which rises and falls at time points, respectively, varying simultaneously as shown in FIGS. 2C and 2D.
The carrier frequency fc (=1/TC) of the PWM signals PA and PB is 16 times of a sampling frequency fs of the digital audio signal Pin, and it will be as follows when fs=48 kHz:fc=16fs=16×48 kHz=768 kHz
One of the PWM signals, PA, from the PWM circuit 11 is supplied to a drive circuit 13 where it will be inverted and not inverted to provide a pair of driving pulse voltages (drive pulse) +PA and −PA as shown in FIG. 3A.
The pulse voltages +PA and −PA from the drive circuit 13 are supplied to gates of switching elements, for example, a pair of n-channel MOS-FETs (metal oxide semiconductor type field effect transistor), 151 and 152, respectively.
In this example, the FETs (field effect transistor) 151 and 152 are included in a push-pull circuit 15 in which the FET 151 is connected at the drain thereof to a power terminal 20 while being connected at the source to the drain of FET 152 which is connected at the source thereof to the ground potential. The power terminal 20 is supplied with a stable DC voltage +VDD as a source voltage. It should be noted that the voltage +VDD is 20 to 50 V for example.
The source of FET 151 and drain of FET 152 are connected to a speaker terminal SP+, to which a speaker 19 is connected at one side thereof, via a low-pass filter 17 including a coil and capacitor.
The circuit construction for the other PWM signal PB from the PWM circuit 11 is similar to that for the PWM signal PA. That is, the PWM signal PB is supplied to the drive circuit 14 where it will be inverted and not inverted to provide a pair of driving pulse voltages (drive pulse) +PB and −PB as shown in FIG. 3B.
The pulse voltages +PB and −PB from the drive circuit 14 are supplied to gates of switching elements, for example, a pair of n-channel MOS-FETs 161 and 162, respectively, included in the push-pull circuit 16.
The source of FET 161 and drain of FET 162 are connected to a speaker terminal SP−, to which the speaker 19 is connected at the other side thereof, via a low-pass filter 18 including a coil and capacitor.
Therefore, when the pulse voltage +PA is “H”, the pulse voltage −PA is “L” and FET 151 turns on while FET 152 turns off. Thus, a voltage VA at the junction between FETs 151 and 152 is the voltage +VDD as shown in FIG. 3C. Reversely, when the pulse voltage +PA is “L”, the pulse voltage −PA is “H” and FET 151 turns off while FET 152 turns on. Thus, the voltage VA is 0.
Similarly, when the pulse voltage +PB is “H”, the pulse voltage −PB is “L” and FET 161 turns on while FET 162 turns off. Thus, a voltage VB at the junction between FETs 161 and 162 is the voltage +VDD as shown in FIG. 3D. Reversely, when the pulse voltage +PB is “L”, the pulse voltage −PB is “H” and FET 161 turns off while FET 162 turns on. Thus the voltage VB is 0.
During a period for which the voltage VA is +VDD and voltage VB is 0, a current i will flow from the junction between FETs 151 and 152 to the junction between FETs 161 and 162 through a line extending from the low-pass filter 17 to the low-pass filter 18 via the speaker 19, as shown in FIGS. 1 and 3E. FIG 3F shows clock signal CLK.
Also, during a period for which the voltage VA is 0 and voltage VB is +VDD, the current i will flow reversely from the junction between FETs 161 and 162 to the junction between FETs 151 and 152 through a line extending from the low-pass filter 18 to the low-pass filter 17 via the speaker 19. During a period for which VA=VB=+VDD and a period for which VA=VB=0, the current i will not flow because the push-pull circuits 15 and 16 form together a bright tied load (BTL) circuit.
Since the period for which the current i flows varies correspondingly to a period for which the original PWM signals PA and PB are rising and the current i is integrated by the low-pass filters 17 and 18 while flowing through the speaker 19, so the current i flowing through the speaker 19 is an analog current corresponding to the level the digital audio signal Pin takes and which has been power-amplified. That is, a power-amplified output will be supplied to the speaker 19.
The circuit shown in FIG. 1 works as a power amplifier. Since FETs 151 and 152, and 161 and 162, amplifies a power by switching the source voltage +VDD correspondingly to the input digital audio signal Pin, so the power amplifier can provide a large output with a high efficiency.
In the circuit constructed as shown in FIG. 1, however, if a speaker cord connected at one end thereof to one of the speaker terminals SP+ and SP− is put in contact with a chassis or metal piece when the speaker 19 is wired to the speaker terminals SP+ and SP−, for example, with the power amplifier kept energized, a large current will flow through either of the push-pull circuits 15 and 16 at the output stage shown in FIG. 1 and FETs 151 and 152, and 161 and 162, included in the push-pull circuit will possibly be damaged.
Also, if the speaker connected, by a lead wire connected to one end thereof, to the speaker terminal SP+ or SP− is put in contact, at a lead wire connected to the other end thereof, with a metallic portion, a large current will flow through the circuit and FETs 151 and 152, and 161 and 162, at the output stage included in the push-pull circuit will possibly be damaged. At this time, the speaker will possibly be broken down (burnt out).
To prevent the above accident, an overcurrent protection circuit is normally provided in the above-mentioned power amplifier. FIG. 4 is a circuit diagram of a conventional power amplifier in which an overcurrent protection circuit is additionally provided.
As shown in FIG. 4, the power amplifier has an overcurrent protection circuit 21 provided between the output-stage push-pull circuits 15 and 16 and the power terminal 20.
More specifically, In the overcurrent protection circuit 21, the power terminal 20 is connected to the ground potential via a capacitor 211, and also via a series circuit composed of a resistor 212 and capacitor 213. The power terminal 20 is connected to the emitter of an overcurrent detection transistor 214. The junction between the resistor 212 and capacitor 213 is connected to the drains of FETs 151 and 161, and the source voltage +VDD is connected to the push-pull circuits 15 and 16 through the resistor 212.
The junction between the resistor 212 and capacitor 213 is connected to the base of the overcurrent detection transistor 214. This transistor 214 is connected at the collected thereof to the base of a transistor 215 whose emitter is connected to the ground potential. The transistor 215 supplies its collector output as an overcurrent detection signal to a microcomputer 22.
When the microcomputer 22 determines, based on the supplied collector output from the transistor 215, that an overcurrent has been detected, it will control the drive circuits 13 and 14 to suspend outputting the drive signals +PA and −PA, and +PB and −PB, and also FETs 151 and 152, and 161 and 162, to always be off.
The overcurrent protection circuit 21 constructed as above functions as will be described below. In the circuit construction shown in FIG. 4, the source voltage +VDD from the power terminal 20 is supplied to the push-pull circuits 15 and 16 through the resistor 212.
In the normal operation of the overcurrent protection circuit 21, since the current i flowing through FETs 151 and 152, and 161 and 162, is smaller in value than a predetermined current and thus the voltage drop by the resistor 212 is small, so the overcurrent detection transistor 214 is off.
On the other hand, when a large current flows through FETs 151 and 152, and 161 and 162, for the above reason, the resistor 212 provides a large voltage drop and thus the overcurrent detection transistor 214 turns on. Thus, the transistor 215 also turns on, and the overcurrent detection signal at the collector of the transistor 215 changes from high to low in level.
Then, since the overcurrent detection output signal is low in level, the microcomputer 22 supplies a control signal to the drive circuits 13 and 14 which will be caused by the control signal to suspend providing outputs. More specifically, receiving the control signal, the drive circuits 13 and 14 will suspend supplying the drive signals +PA and −PA, and +PB and −PB, to FETS 151 and 152, and 161 and 162. Thus, FETS 151 and 152 and 161 and 162 are all turned off, and no overcurrent will flow. Therefore, FETS 151 and 152, and 161 and 162, and the speaker 19 are protected.
Note that when the speaker 19 is connected to the speaker terminals SP+ and SP− and it is PWM-driven, the power amplifier will provide an output of more than several to 100 W.
In the aforementioned detection circuit construction, the source voltage +VDD is supplied to the push-pull circuits 15 and 16 through the overcurrent detection resistor 212. In the normal mode of operation, a current corresponding to an audio signal current i flowing to the speaker 19 flows through the resistor 212, so that the source voltage (voltage at the drains of FETS 151 and 161) of the push-pull circuits 15 and 16 will vary.
Thus, the circuit construction shown in FIG. 4 cannot provide minimum and maximum power amplifier outputs at a desired ratio.